1. Field of the Invention
The present invention relates to an image TFT array. More particularly, the present invention relates to a method of fabricating an image TFT array of a direct X-ray image sensor and the image TFT array.
2. Description of the Prior Art
There have been proposed systems and methods for detection of static and/or dynamic X-ray images. These digital X-ray systems and methods provide digital representations of X-ray images in which the X-ray image is recorded as readable electrical signals, thus obviating the need for films and screen in the imaging process. Digital X-ray systems typically rely on direct conversion of X-rays to charge carriers or alternatively indirect conversion in which X-rays are converted to light which is then converted to charge carriers.
FIG. 1 shows a schematic cross sectional view of a direct conversion digital detector. Direct conversion approaches typically use an X-ray sensitive photoconductor 2 such as amorphous Se, Cd, Ta, and the like overlying a solid state element 4. The solid state element 4 comprises a solid state array having thin-film-transistors (TFTs) 6 coupled to storage capacitors 8. The photoconductor 2 generates electron-positive hole pairs (EHP) upon reception of energy, such as x-rays, incident through a top electrode 1. The positive holes accelerated by several thousand volts between the top electrode and the ground plane of the TFT array are collected by charge collection electrodes (CCE) 3 which charge storage capacitors 8. When the gate channel 7 of TFT 6 is open, discharging currents flow through the channel and the charges are converted directly into the digital signal by the external read out circuit connected to the end of the data line 5.
In FIG. 2, a top view of an image TFT array for a direct X-ray image sensor is shown. FIG. 3 is a sectional view taken along line A-A′ and line B-B′ of FIG. 2. As shown in FIGS. 2 and 3, each pixel of the prior art includes a substrate 10, a gate line 12, a gate electrode being a part of the gate line, an insulation layer 14, an island structure 16, a drain electrode 18, a source electrode 20, a data line 13 connecting the drain electrode 18, a common line 22, a passivation layer 24, a bottom electrode (a pixel electrode) 30, an insulation layer 32, and a top electrode (a charge collector electrode) 36. The source electrode 20 is electrically connected to the top electrode 36 through a via hole 26 by the bottom electrode 30. The common line 22 is connected to the bottom electrode 30 through a via hole 28 penetrating the passivation layer 24 on the common line 22.
The method for fabricating the above image TFT array includes seven steps of photolithography and etching. That is, the conventional method requires seven masks. The first photolithography step defines the gate line 12 including the gate electrode. And then an insulation layer 14 is deposited on the substrate 10 and the gate line 12 and the second photolithography step is performed to define the island structure 16. After the third photolithography step defines the common line 22, the source electrode 20, the drain electrode 18, and the data line 13, an passivation layer 24 is deposited and the fourth photolithography step is performed to define the via holes 26 and 28 simultaneously, as well as to remove the passivation layer 24 on the source pad of the data line 13, and remove the passivation layer 24 and the insulation layer 14 on the gate pad of the gate line 12. The source pad and the gate pad are positioned in the periphery of the pixel area for electrically connecting the driver ICs. Since the removals are performed in one step and the passivation layer 24 on the source pad is thinner than the total of the passivation layer 24 and the insulation layer 14 on the gate pad, the metal layer of the source pad of the data line is easily over etched. Especially when a Mo/Al/Mo (molybdenum/aluminum/molybdenum) layer is used as the second metal layer, the top Mo layer suffers from serious loss. And the fifth photolithography step defines the bottom electrode (the pixel electrode) 30 and fills the same material in the via hole 26. Then, a capacitor insulation layer 32 is formed and the sixth photolithography step defines the via hole 34. Finally, the seventh photolithography step defines the top electrode (the charge collector electrode) 36, as shown in FIG. 3.
In the above conventional method, the capacitor insulation layer, such as SiNx, must be formed at a relatively low temperature to avoid the damage of the TFT structure which has already been formed. Thus, the resulting SiNx layer has an inferior quality for serving as a dielectric layer in a capacitor, in addition to the problem of over etching mentioned above.